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Intel describes 22nm SoC process at IDF

Posted on Friday, September 14 2012 @ 12:08:10 CEST by


Intel talked about its 32nm Medfield SoC at the IDF in San Francisco and confirmed that the 22nm Bay Trail SoC will debut next year at the IDF in Beijing. The chip giant didn't discuss the features of this new SoC for tablets and smartphones, but did reveal details about P1271, the new 22nm SoC process that will be used to manufacture Bay Trail.

The new process differs from Ivy Bridge's 22nm process by offering lower leakage logic transistors, higher voltage I/O transistors, denser upper layer interconnects, and a set of precision resistors, capacitors and inductors.
“It’s not one set of features, but a menu of feature options—transistors, I/O, interconnects, passive elements and embedded memory,” Bohr said. “The [SoC] transistors go down to much lower leakage levels, but give up some performance,” he said.

The process has significantly better analog characteristics than Intel’s current 32-nm planar process. Designs make heavy use of 80-nm pitch features in lower metal layers, because they are the smallest features Intel can make at 22 nm without needing double patterning, he added.
Intel 22nm SoC process slide

Intel 32nm vs 22nm performance and leakage

Source: EE Times



 



 

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