Posted on Friday, September 21 2012 @ 17:26 CEST by Thomas De Maesschalck
Chip designer ARM will discuss its "big-little" power saving method at the upcoming ARM TechCon conference in Santa Clara, California between October 30 - November 1. This technique aims to increase power efficiency by bundling a high-performance processor core with a power-efficiency tuned model. The company will also reveal the first processors that use it.
The idea of big-little was first discussed by ARM in 2011 at the announcement of the Cortex-A7 processor core. It is the method whereby a pairing of a high-performance processor core and a power-efficiency tuned processor core could share processing duties in a cache-coherent combination with an overall power-saving advantage. The Cortex-A15 and Cortex-A7 were introduced as the first big-little pairing that might use this technique with the forecast that chips including such pairings would appear in 2013.
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According to the presentation abstract the first devices employing the big-little design style have arrived in silicon, which means that the presentation can report measured power savings and performance capabilities of big-little systems during such applications as web browsing, gaming, and background mobile phone and tablet computer activity. The presentation also set to discuss new CPUs on the ARM roadmap that will support the big-little approach.
Source: EE Times
