“It’s clear planar silicon as we know it ends at about the 20 nm node, then there will be a race to different architectures and materials or combinations of both,” said Suresh Venkatesan, senior vice president of technology development at Globalfoundries, moderating an evening panel at the International Electron Devices Meeting.
An IBM expert challenged that statement, showing a 10-nm planar process.
Panelists argued for an assortment of options including FinFETS, germanium, III-V materials, tunnel FETs, nanowires and fully depleted silicon-on-insulator. All sides agreed just what defines a new node is increasingly unclear.
Semiconductor experts discuss future of process technology
Posted on Friday, December 14 2012 @ 12:05 CET by Thomas De MaesschalckEE Times has published a summary of a IEDM debate on the future of semiconductor technology, you can read it over here.
