Posted on Wednesday, December 19 2012 @ 12:50 CET by Thomas De Maesschalck
Globalfoundries is reportedly considering to add a third manufacturing option to follow conventional bulk planar CMOS: super-steep retrograde well (SSRW). This chip manufacturing technique creates a ground plane under a transistor using a doping technique. Full details
at EE Times.
If adopted, the SSRW process would likely be in addition to previously announced 14XM 14-nm FinFET process due in 2014 and its licensing of 28-nm and 20/14-nm fully-depeleted silicon on insulator (FD-SOI) manufacturing process technology from STMicroelectronics. However, it could potentially compete with both processes for design wins.
The possibility that Globalfoundries could pursue all three options underscores the challenges facing conventional bulk planar CMOS.
Globalfoundries CEO Ajit Manocha referred to SSWR in a presentation during the International Electron Devices Meeting (IEDM) in San Francisco earlier this month. Manocha said SSWR – alongside FinFETs and FDSOI – represents a manufacturing option for fully depleted transistor architectures and that fully depleted transistors offer superior low voltage and electrostatic performance along with scalability.
