Posted on Monday, August 12 2013 @ 16:52 CEST by Thomas De Maesschalck
While Intel's current-generation Sandy Bridge-E Core i7 series is actually an eight-core Sandy Bridge-EP Xeon E5 with two cores and outside QPI disabled, it appears the upcoming Ivy Bridge-EP is based on a more compact, native six-core Xeon design:
Guess what, the Ivy Bridge-EP Xeon E5 v2 series has three different dies in its spread: one of them is actually a native, compact, six-core die with 15 MB L3 cache – the other two being 10-core 25 MB L3 dies, and 12-core 30 MB L3 dies. That smallest die is the base for the six-core Ivy Bridge-E Core i7 LGA2011 series, so there are no ‘turned off’ cores off a larger die here. You still have the quad-channel DDR3-1866 memory controller, which should give more memory O/C headroom than the predecessor, and the two QPI channels from the Xeon die necessary for multi-socket operation are turned off on the desktop, of course.
The impact? A big plus compared to the old crippled gigantic eight-core 32 nm die with three out of four of its cores enabled. Now, it is a comparatively small six-core die without the huge graphics portion, but with lotsa PCI-E v3.0 and very wide memory should have very good O/C potential in the production version, since Intel had an extra year plus to solve any leakage problems on the 22 nm FinFET process. Also, we assume, Intel will continue to use soldered heat spreader solution on high end LGA2011 chips, rather than the el cheapo toothpaste seen on the desktop Ivy Bridge chips.
