36-core CPU solves bus clogging with router on each core

Researchers showed off an experimental 36-core "network-on-chip" processor design at the International Symposium on Computer Architecture. What makes this processor so special is that each core features its own router, data travels between the cores in packets of fixed size instead of going through a single bus.

Li-Shiuan Peh, the Singapore Research Professor of Electrical Engineering and Computer Science at MIT, explained at the event that by making the processor act like a little Internet you can solve the issue of cores idling as they're waiting for the bus to free up. The more cores you have the bigger the bus problem becomes, whereas with this little Internet on a chip each core can reach its neighbors really quickly, and there are also multiple paths to the destination so the data can avoid congested routes. You can read more details at MIT.

Today's processors are connected by a single wire, and feature between 2 and 6 cores, with the multiple cores needing to talk to each other through exclusive access to the bus. But, this way won't work as the core count increases, as the other cores will be waiting for the bus to free up, rather than performing the duties you've set it out to do. With the network-on-chip, each and every CPU core is connected only to those that are directly next to it. Bhavya Daya, an MIT graduate student in electrical engineering and computer science explains: "You can reach your neighbors really quickly. You can also have multiple paths to your destination. So if you're going way across, rather than having one congested path, you could have multiple ones".

Source: TweakTown