TSMC says Moore's Law not slowing down, talk 7nm and 10nm

Cadence sat own with Suk Lee, Senior Director, Design Infrastructure Marketing Division of TSMC, to talk about the future of chip manufacturing. Lee said it doesn't look like Moore's Law is going to end any time soon but acknowledged this requires substantial continued investment. He added that TSMC is expected to do over 50 product tapeouts on the 16nm process this year and added that high-volume production will kick off in Q3 2015 with meaningful revenue contribution starting in Q4 2015.

The 10nm process is expected to be fast-rising as well, TSMC is working with over 10 customers on their 10nm product design and volume production is expected to start in 2017. Full details over here.

Q: Engineers apply lessons of any process node ramp to the subsequent process. What did 16nm learn from 20 and what is 10nm learning from 16?

Lee: The blogosphere about two years ago had some commentary about "wow 20 v. FinFET--that seems like a mistake." We had a conscious strategy, which was creating the ultimate planar technology with 20nm SoC and then spinning out 16nm FinFET with essentially the same metal stack. That was a great risk mitigation strategy for TSMC. We had a very advanced metal stack with a set of leading customers who wanted to squeeze every last drop out of planar. So 20nm turned into a great deal of business for us. We didn't have to take on two challenges at the same time—developing this complex metal system and bringing up FinFET. We've enjoyed the manufacturing learnings on the metal system, and that has made the ramp on 16FF much easier. You've seen in the press some of our competitors are struggling with their FinFET technology yields. Our technology has moved forward very smoothly.

Q: So how about from 16 to 10nm?

Lee: The thing that carries forward from 16 to 10nm is basic FinFET learning obviously, but also the techniques that we've refined on 16nm to handle multiple patterning segue smoothly into 10nm.

In general, one of the things we've done in the past four years is that we've engaged with the EDA/IP ecosystems earlier and earlier. We used to engage at SPICE 1.0. The pace of technology development and the pace of our customers' product cycles means that we've had to engage much earlier than in the past. For the ecosystem, one of the things that started at 28 and came to full fruition at 16 was that we mutually learned how to do process and full product all in parallel. That's really going to be a critical thing for 10. We're working with the ecosystem on 10. Our customers already are working on 10nm product designs. That's the result of the learning that we applied with the ecosystem on 28, 20, and 16 on how to do concurrent ecosystem and process bring up. That's enabled us to engage very quickly at 10nm.