Eight question answered about FD-SOI process technology

Posted on Thursday, Jul 02 2015 @ 11:31 CEST by Thomas De Maesschalck
EE Times has written an interesting piece about FD-SOI (Fully Depleted Silicon On Insulator), in which they answer eight questions about this process technology. You can read it over here.

One big questions for example is that if FD-SOI is so good, why isn't Intel doing it? The site explains that as an integrated device manufacturer, Intel had to make a choice in 2004 between FinFET or planar FD-SOI. The latter wasn't even a real choice at that point so the chip giant went FinFET.
Chenming Hu, professor of microelectronics at University of California, Berkeley, wrote papers on FinFETs and ultra-thin body silicon on insulator (UTB-SOI) as early as the late 1990’s. Hu, chief technology officer of TSMC between 2001 and 2004, recently wrote in Advanced Substrate News, “When we first invented the [FD-SOI] concept in 2000, the availability of SOI substrates [that requires a very thin top layer of silicon] was the major obstacle. The final silicon layer thickness had to be about a quarter to a third of the gate length.”

As an integrated device manufacturer, Intel had to make a choice in 2004 between FinFET or planar FD-SOI. At that point, FD-SOI wasn’t even a real choice.

Hu noted, later, “Soitec has surmounted the wafer challenge and with that, commercial production can now become a reality,” but that reality didn’t really arrive until a few years ago. For fabless chip companies, FD-SOI is a real choice today. But for Intel, that train has already left the station.
wafer cost estimates


About the Author

Thomas De Maesschalck

Thomas has been messing with computer since early childhood and firmly believes the Internet is the best thing since sliced bread. Enjoys playing with new tech, is fascinated by science, and passionate about financial markets. When not behind a computer, he can be found with running shoes on or lifting heavy weights in the weight room.



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