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AMD Boltzmann Initiative will be able to port large parts of NVIDIA CUDA code

Posted on Monday, November 16 2015 @ 21:49:57 CET by


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AMD announced its Boltzmann Initiative, a new project to bolster the adoption of its HSA capabilities on AMD FirePro workstation cards. Among other things, this includes a new HIP tool that can reportedly, in many cases, port up to 90 percent or more of CUDA code written for NVIDIA GPUs to C++ by HIP with the final 10 percent converted manually in the C++ language. An early access program for the Boltzmann software is expected in the first quarter of 2016.

So why is it called the Boltzmann Initiative? It seems to be a reference to the restricted Boltzmann machine, a type of neural network designed for deep learning.
Building on its strategic investments in heterogeneous system architecture (HSA), AMD (NASDAQ:AMD) announced a suite of tools designed to ease development of high-performance, energy efficient heterogeneous computing systems. The "Boltzmann Initiative" leverages HSA's ability to harness both central processing units (CPU) and AMD FirePro™ graphics processing units (GPU) for maximum compute efficiency through software. The first results of the initiative are featured this week at SC15 and include the Heterogeneous Compute Compiler (HCC); a headless Linux® driver and HSA runtime infrastructure for cluster-class, High Performance Computing (HPC); and the Heterogeneous-compute Interface for Portability (HIP) tool for porting CUDA-based applications to a common C++ programming model. The tools are designed to drive application performance across markets ranging from machine learning to molecular dynamics, and from oil and gas to visual effects and computer-generated imaging.

"AMD's Heterogeneous-compute Interface for Portability enables performance portability for the HPC community. The ability to take code that was written for one architecture and transfer it to another architecture without a negative impact on performance is extremely powerful," said Jim Belak, co-lead of the U.S. Department of Energy's Exascale Co-design Center in Extreme Materials and senior computational materials scientist at Lawrence Livermore National Laboratory. "The work AMD is doing to produce a high-performance compiler that sits below high-level programming models enables researchers to concentrate on solving problems and publishing groundbreaking research rather than worrying about hardware-specific optimizations."

New Compiler for Heterogeneous Computing
The promise of combining multi-core, serial processing CPUs with parallel-processing GPUs to maximize compute efficiency is already being seen in the industry, as driven by the Heterogeneous Systems Architecture (HSA) Foundation that counts AMD as a founding member. One of the goals for HSA is easing the development of parallel applications through use of higher level languages. The new AMD "Boltzmann Initiative" suite includes an HCC compiler for C++ development, greatly expanding the field of programmers who can leverage HSA. The new HCC C++ compiler is a key tool in enabling developers to easily and efficiently apply the hardware resources in heterogeneous systems. The compiler offers more simplified development via single source execution, with both the CPU and GPU code in the same file. The compiler automates the placement code that executes on both processing elements for maximum execution efficiency.

"Just as our customers are excited about our hardware innovation, including the introduction of the first GPU with High Bandwidth Memory this year and our new x86 core architecture coming next year, our innovations in software development are equally as important to them," said Mark Papermaster, senior vice president and chief technology officer, AMD. "The challenge has always been to unlock the hardware's capabilities and make them easily accessible to developers working to solve difficult problems. AMD's newest offering provides the keys to more readily access our parallel computing engines – both multicore CPUs and GPUs – and to make these benefits available to the mainstream of developers across a broad spectrum of computing platforms, from embedded to supercomputing."

Linux Driver and Runtime Focused on the Needs of HPC Cluster-Class Computing
To complement the new compilation tools, AMD has developed a new HPC-focused driver and system runtime. This new headless Linux driver brings key capabilities to address core high-performance computing needs, including low latency compute dispatch and PCIe® data transfers; peer-to-peer GPU support; Remote Direct Memory Access (RDMA) from InfiniBand™ that interconnects directly to GPU memory; and Large Single Memory Allocation support.

HIP-ifying CUDA Application to Run on AMD GPUs
To bring applications written for CUDA onto AMD platforms, AMD announces the new HIP tool. AMD testing shows that in many cases 90 percent or more of CUDA code can be automatically converted into C++ by HIP with the final 10 percent converted manually in the widely popular C++ language. This greatly expands the installed hardware base available to run what were formerly exclusively CUDA-based applications. At SC15, AMD is demonstrating the potential for HIP, running the CUDA-generated Rodinia benchmark suite on AMD GPUs.

Availability
An early access program for the "Boltzmann Initiative" tools is planned for Q1 2016.

Other News at SC15
AMD continues to support the open standard OpenCL™ programming language, giving developers low-level GPU programming and optimization capabilities. AMD has expanded its GPU compute libraries, allowing developers to easily accelerate compute-intensive functions by leveraging GPU compute. The addition of HcBLAS and HcFFT builds on work done with clBLAS, clFFT, clSPARSE and clRNG for OpenCL. The libraries include functions that are widely used in scientific computation and data science.




 



 

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