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Intel to discuss the 65nm process this week

Posted on Tuesday, August 23 2005 @ 02:33:50 CEST by


Intel has its IDF running this week so expect tens of news articles regarding Intel's plans this week. One of them is the company's plan to start using a new 65nm process for applications that require lower power consumption. It looks like Intel developed two versions of its 65nm process: the P1264 which will be introduced as the successor to the 90nm process and incorporated for high-end process while the new P1265 will be utilized for embedded processors. The P1265 process uses SRAM cells with a power leakage 300 times lower than the P1264 technology.

However, there are a few disadvantages. The P1265 needs more space and won't clock as high as the P1264 based processors. The P1265 won't fit for applications that mainly require performance, but it will be perfect for embedded processors like the Xscale-series.

Other details about the 65nm process will be announced later this week. This process will use the second generation strained silicon and will also incorporate new innovations. It will use 'sleep transistor' to disable cache blocks and there's also a technique called 'stack effect' which will make power flow through multiple places, instead of one place, to a channel. This will mean a five to ten times lower power leakage. The 65nm process will also use additional transistors to lower the power consumption.

Intel says that by running two transistors at half speed a task will be performed just as fast as a single block at full speed, while cutting power consumption with 75 percent. This requires multiple voltages, but that's also a feature of the 65nm process.

Source: Tweakers


 



 

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