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Intel unveiled Yonah details

Posted on Wednesday, August 24 2005 @ 17:45:38 CEST by


Yesterday at the IDF Ronny Korner, Intel's CPU Validation Manager at Intel Israel, talked about the upcoming mobile Yonah processor. This CPU will be a dual-core 65nm part, 90.33mm square with 151 million transistors, 2MB shared cache, VT and SSE3 support along with a 667MHz FSB, he said. This processor has been optimized by power and performance, and the system will see the Yonah as a single entity.

Korner says full dual-core optimization means Yonah will feature low power, smart thermal and power management, and elimination of redundant logic.
He said that improving media performance is a complex architecture task. Intel profiled a lot of apps running on Dothan and what it learned from these, it improved the architecture to optimize them. Better decoder bandwidth meant the Micro OP Fusion was extended to SSE2 LD-OP instructions, and the 128 bit SSE2 instructions are now handled by all three decoders which Korner claimed gives up to three times decoder bandwidth.
Both Yonah cores use the full size shared L2 cache, with shared data accessed from te cache minimizing the buss traffic. The chip also includes dynamic cache allocation.

the Yonah die

Korner further added Yonah will deliver a longer battery life over the previous Dothan and Banias Pentium M cores by utilizing techniques such as Vcc cache design. Each core also has its own sleep state, controlled by the OS using the new MWAIT (Cx) instruction.

There's also a derivative of the Yonah targeted at low power blade and rack servers. This will be Sossaman, supporting up to 64GB of memory. More info at The Inquirer


 



 

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