MIT researchers find more efficient way to make sub-10nm chips

MIT researchers announced the discovery of a new self-assembly technique that could lead to a simpler and cheaper production process for the volume production of sub-10nm semiconductors. Rather than using complex lithography like the EUV that will be adopted in the coming years, the MIT researchers propose a different, polymer-film based method that should be compatible with existing machines, and that uses well-known materials.

For the last few decades, microchip manufacturers have been on a quest to find ways to make the patterns of wires and components in their microchips ever smaller, in order to fit more of them onto a single chip and thus continue the relentless progress toward faster and more powerful computers. That progress has become more difficult recently, as manufacturing processes bump up against fundamental limits involving, for example, the wavelengths of the light used to create the patterns.

Now, a team of researchers at MIT and in Chicago has found an approach that could break through some of those limits and make it possible to produce some of the narrowest wires yet, using a process with the potential to be economically viable for mass manufacturing with standard types of equipment.

Full details at MIT.