TSMC enters 7nm volume production, reveals 5nm details

TSMC announced it is now doing volume production of 7nm chips, the foundry expects to do over 50 tape-outs this year. The 7nm process delivers 35 percent higher performance or 65 percent lower power consumption, and has a 3x gain in routed gate density. However, the gains are getting smaller and smaller. For the company's N7+ node with EUV, there will be no apparent speed gains. This node promises 20 percent higher density and 10 percent lower power consumption, but will require new standard cells.

So how are the 7nm EUV yields? TSMC claims test yields of 256Mbit SRAM at N7+ are as good as the yields that were achieved for the early 7nm node.

TSMC has validated in silicon what it calls foundation IP for N7+. However, several key blocks will not be ready until late this year or early next year, including 28-112G serdes, embedded FPGAs, HBM2 and DDR5 interfaces.

Expect 10-20 percent more effort laying out IP for the EUV process, said Cliff Hou, vice president of R&D for design and technology platforms. “We developed a utility to migrate IP with incremental effort,” he said.

Fully certified EDA flows for N7+ will be ready by August. Meanwhile, yields of a test 256-Mbit SRAM at N7+ are as good as yields were for the early 7nm node, he said.

We also learn TSMC intends to kick off 5nm risk production in late 2019, this process will focus on mobile and high-performance computing chips. Compared with the regular (non-EUV) 7nm node, the 5nm process is projected to have a 15 percent performance boost or 20 percent lower power consumption, and a 1.8x greater density. Basically, for future nodes, EUV will become necessary to achieve the same scaling advantage as past nodes. More details at EE Times.