Posted on Wednesday, February 20 2019 @ 12:32 CET by Thomas De Maesschalck
Over at the International Solid State Circuits Conference in San Francisco, Toshiba revealed details of a new 96-layer, 4-bits-per-cell 3D NAND memory chip with a capacity of 1.33Tb. The QLC chip stores 8.5Gb/mm², a bit density over 40 percent better than a 512Gb TLC 3D NAND memory chip also presented at the conference.
The device features a die size of 158.4mm2. It utilizes a modified source-bias-negative-sense scheme, allowing for deep negative threshold voltage while maintaining a low supply voltage, according to Noboru Shibata, a Toshiba design engineer who presented the paper at ISSCC. The paper was authored by Shibata and a group of engineers from Toshiba and Western Digital.
More details
at EE Times.
