AMD plans to stack DRAM and SRAM on its CPUs

At a recent high-performance computing (HPC) event, AMD revealed it's working on technology to integrate 3D stacked DRAM and SRAM in its processors. By stacking this memory on top of its CPUs, AMD aims to achieve higher performance.

AMD SVP and GM Forrest Norrod talked about the firm's 3D stacking plans at the Rice Oil and Gas HPC conference. Part of AMD's Working Beyond Moore's Law initiative, the company sees stacked memory architectures as one of the most important steps in the near term, to ensure future CPUs can continue to deliver more performance.

This on-die stacked memory approach would differ from normal package-on-package (PoP) implementations that simply place two finished packages atop one another, as seen above with a Samsung chip. In this example, the DRAM package connects through two additional rows of BGA connectors that ring the underlying chip. These BGA connectors carry the data transferred between the two chips. As with any standard design, the logic resides on the bottom of the stack due to its need for more connectors, but the two die are not connected directly. As such, the PoP approach provides the utmost in density, but it isn't the fastest option.

More at Tom's Hardware. Intel is also moving towards this path, with its Foveros 3D packaging technology.