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May 25, 2019 
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TSMC sees path to 1.4nm and below

Posted on Friday, May 17 2019 @ 11:22:54 CEST by


TSMC logo
At the Hot Chip symposium in August, TSMC corporate research VP Philip Wong will be giving a keynote about the future of process technology. Scheduled for August 20th, this talk will discus the scaling to 5nm, 3nm, 2nm, 1.4nm, and even below a nanometer:
Abstract: The power-performance-area (and cost) advances in the last five decades have mostly been achieved through dimensional scaling of the transistor. What will the semiconductor industry do after dimensional scaling of the silicon transistor crosses the nanometer threshold, from 16/12 nm, 10 nm, 7 nm, 5 nm, 3 nm, 2 nm, 1.4 nm to sizes below a nanometer? Will these advanced logic technologies continue to provide the energy efficiency required of future computing systems? Will new applications and computation workloads demand new device technologies and their integration into future systems? These are some of the most pressing questions facing the semiconductor industry today.

The path for IC technology development going forward is no longer a straight line. The need for out-of-the-box solutions ushers in a golden age of innovation. I will give an overview of the memory and logic device innovations that are in the research pipeline today. Future electronic systems require co-innovation of the computing architecture and device technology. I will speculate on how they will be integrated into future electronic systems.




 



 

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