PCI Express battlefield explored

In a new article, Trias Research analyst Kevin Krewell explores the future of PCI Express as well as other connection standards (which may or may not run on PCIe). PCI Express 4 just hit the market and PCI Express 5 is expected to follow in a year or two. The focus is on making each PCI Express lane faster, as an expansion of the bit width of PCI Express is not really an option as this would result in an increase in packaging pins and board space.

At some point in the future, coax or optical cabling may be needed, but for the foreseeable future PCI Express will continue to get performance boosts using the current, cheap copper interconnects.

PCIe also is a platform for other standards to compete because it’s a primary link among CPUs, GPUs, FPGAs and accelerators for heterogeneous computers. Even though there are other proprietary and standards-based buses such as NVLink and OpenCAPI, most still rely on the base technology of the PCIe physical layer.

In particular, the timing of the new PCIe generations has a direct impact on two competing accelerator connection standards that allow CPUs and accelerators to share memory—the Cache Coherent Interface for Accelerators (CCIX) and the Compute Express Link (CXL).

Full details over here.