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Intel Xe is biggest graphics instruction overhaul since 2004

Posted on Tuesday, September 10 2019 @ 10:29:17 CEST by

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In a merge request on Gitlab, Intel Linux graphics team guy Francisco Jerez reveals that Gen12 graphics will be one of the most "in-depth reworks" of the Intel execution unit (EU) instruction set architecture (ISA) since the launch of the original i965 in 2004. The next-gen graphics architecture from Intel will be used by the Xe discrete video cards as well as integrated graphics in the Tigerlake processor line.
This merge request implements support for the Gen12 (Tigerlake) ISA in the i965/Iris compiler back-end.

Gen12 is planned to include one of the most in-depth reworks of the Intel EU ISA since the original i965. The encoding of almost every instruction field, hardware opcode and register type needs to be updated in this merge request. But probably the most invasive change is the removal of the register scoreboard logic from the hardware, which means that the EU will no longer guarantee data coherency between register reads and writes, and will require the compiler to synchronize dependent instructions anytime there is a potential data hazard...
The first Intel Xe products are expected in 2020.



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