TSMC 5nm is 1.84x denser than 7nm

WikiChip goes in-depth about the latest process node details that were recently revealed by TSMC, you can read the full piece over here. The Taiwanese foundry revealed that its N5 process will offer 1.84x greater transistor density than N7.

For a typical mobile SoC with 60 percent logic, 30 percent SRAM and 10 percent analog I/O, this should result in a chip size reduction of 35 to 40 percent. TSMC also reiterated that 5nm will offer 15 percent higher speed at the same power consumption, or 30 percent lower power consumption at the same speed.

TSMC's 5nm node is expected to enter volume production in April or May. It will be world's densest process in terms of transistor density and SRAM density. Samsung's 5nm process will not be able to match TSMC's 5nm as the 5nm node from the South Korean giant will barely offer density improvement. Intel's 7nm process is expected to be denser than TSMC's 5nm, but the 7nm node from Intel isn't expected to hit mass production until late next year.

TSMC execution has been remarkable the last couple of nodes. Since their 16 nm node, each process node has been ramping quicker than its predecessor. N7 was the company’s quickest-ramping node with fastest defect density reduction ever. TSMC says it expects its N5 node to ramp even quicker. 5-nanometer entered risk production in March 2019. The process is expected to ramp in Q2 this year – likely in April or May. When ramped, this will be the densest process in terms of both transistor density and SRAM density – leapfrogging both Samsung and Intel. Samsung 5-nanometer is only slightly denser than their 7-nanometer and is not competitive with TSMC 5 nm. Samsung’s next big jump is their 3-nanometer node. Intel will likely capture the density lead with their 7-nanometer node, however, that node isn’t coming until late next year – a solid 1.5 years behind.