The fresh information is that Zen 3 reportedly delivers a 10-15 percent IPC gain on a single thread, which is about on par with the IPC increase of Zen 2. That's a bit lower than what earlier rumors suggested. A large part of the IPC increase originates from a reworked front end.
Zen 3 will get double the L3 cache per CCX, but total L3 cache remains the same as each compute die now has only one CCX instead o two:
Additionally, Zen 3 will double the L3 cache per CCX, but since there is now only 1 CCX per compute die instead of 2, the level of L3 cache remains the same at 32 MB. Unfortunately, there will be no 48 MB or 64 MB L3 caches with Zen 3, which I’m sure is disappointing for some. L3 cache latency has slightly increased, presumably due to the CCX redesign but this is offset by the fact that cores now have equal access to all the L3 cache on the same die; no more spikes in latency from grabbing data off of another CCX. This will make the performance more consistent, a problem that Zen 2 mostly fixed but not entirely.AMD has A0 engineering samples of the "Milan" EPYC server processor but these are still in early testing phases. The site heard that current samples do not have working SMT. B0 samples are expected around September and an actual product launch will probably be late 2020 or early 2021. As always, take these rumors with a grain of salt.
Last but not least, AdoredTV claims Zen 4 will likely be a 5nm part with more cores, a new socket, 1MB L2, AVX-512 support, and further IPC gains. Nothing really groundbreaking here.