DDR5 gets finalized - double the bandwidth, higher density, on-die ECC and on-DIMM voltage regulator

JEDEC finally finished the DDR5 specification. The new memory specification doubles the maximum supported data rate to 6.4Gbps and enables much greater memory density. Of course, this doesn't mean we'll see DDR5-6400 modules at launch, but it does mean you can expect those modules (as well as much faster) somewhere down the road. JEDEC calls for DDR5-4800 at launch so that's 50 percent more than the official 3.2Gbps peak of DDR4.

Whereas DDR4 supported a maximum die density of 16Gb, this is now increased to a maximum of 64Gb for DDR5. The maximum memory module size for typical UDIMMs will be 128GB, a fourfold increase. For servers, a maximum memory module capacity of 2TB isn't out of the question.

Besides higher capacity and more bandwidth, DDR5 also packs some other changes under the hood. While DDR4 uses a single-channel 64-bit data channel per DIMM, DDR5 switches to two 32-bit data channels. Each channel has double the burst length of DDR4, it's now 16 bytes per channel, which doubles the effective bandwidth.

Other changes include on-die ECC (error-correcting code), which improves the reliability of memory chips. This is not the same as the DIMM-wide ECC used by server memory, but it is the first time we're seeing a form of ECC that will also be used by the consumer versions of DDR.

Power efficiency is improved as DDR5 requires just 1.1V, versus 1.2V for DDR4. Also interesting is that DDR5 will feature on-DIMM voltage regulators. Voltage regulation for DDR4 is handled by the motherboard but with DDR5 this will become the responsibility of the memory modules.

The first products are expected in 2021 but it's unknown when DDR5 will trickle down to the consumer market. Based on current leaks and rumors, it seems we should not expect consumer-level AMD or Intel platforms with DDR5 support before 2022.

JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, today announced the publication of the widely-anticipated JESD79-5 DDR5 SDRAM standard. The standard addresses demand requirements being driven by intensive cloud and enterprise data center applications, providing developers with twice the performance and much improved power efficiency. JESD79-5 DDR5 is now available for download from the JEDEC website.

DDR5 was designed to meet increasing needs for efficient performance in a wide range of applications including client systems and high-performance servers. DDR5 incorporates memory technology that leverages and extends industry know-how and experience developing previous DDR memories. The standard is architected to enable scaling memory performance without degrading channel efficiency at higher speeds, which has been achieved by doubling the burst-length to BL16 and bank-count to 32 from 16. This revolutionary architecture provides better channel efficiency and higher application level performance that will enable the continued evolution of next-generation computing systems. In addition, the DDR5 DIMM has two 40-bit fully independent sub-channels on the same module for efficiency and improved reliability.

New features, such as DFE (Decision Feedback Equalization), enable IO speed scalability for higher bandwidth and improved performance. DDR5 supports double the bandwidth as compared to its predecessor, DDR4, and is expected to be launched at 4.8 Gbps (50% higher than DDR4’s end of life speed of 3.2 Gbps).

Additional features include:
- Fine grain refresh feature: as compared to DDR4 all bank refresh improves 16 Gbps device latency. Same bank self-refresh offers better performance by enabling some banks to refresh while others are in use.
- On-die ECC and other scaling features enable manufacturing on advanced process nodes.
- Improved power efficiency enabled by Vdd going from 1.2V to 1.1V as compared to DDR4.
- Use of the MIPI® Alliance I3C Basic specification for system management bus.
- At the module level, voltage regulator on DIMM design enables pay as you go scalability, better voltage tolerance for improved DRAM yields and the potential to further reduce power consumption.

“With several new performance, reliability and power saving modes implemented in its design, DDR5 is ready to support and enable next-generation technologies,” said Desi Rhoden, Chairman JC-42 Memory Committee and Executive VP Montage Technology. “The tremendous dedication and effort on the part of more than 150 JEDEC member companies worldwide has resulted in a standard that addresses all aspects of the industry, including system requirements, manufacturing processes, circuit design, and simulation tools and test, greatly enhancing developers’ abilities to innovate and advance a wide range of technological applications.”