Intel sees way to double transistor density with nanosheet stacking

Posted on Thursday, December 31 2020 @ 10:39 CET by Thomas De Maesschalck
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At this week's IEEE International Electron Devices Meeting (IEDM), Intel revealed some of the results of research into the stacking of nanosheet transistors. While this technology is still far from being production ready, Intel says it holds a lot of promise as it could essentially double the transistor density of future processors. Robert Chau, Intel senior fellow and director of components research, claims they came up with a "very practical flow with respectable results". Full details at IEEE Spectrum.
The scheme starts by using what’s widely agreed to be the next generation transistor structure, called variously nanosheet, nanoribbon, nanowire, or gate-all-around device depending on who’s involved. Instead of the main part of the transistor consisting of a vertical fin of silicon as it does today, the nanosheet’s channel region consists of multiple, horizontal, nanometers-thin sheets stacked atop one another. stacked nanosheet transistors

Intel engineers used these devices to build the simplest CMOS logic circuit, an inverter. It requires two transistors, two connections to power, one input interconnect, and one output. Even when the transistors sit side-by-side, as they do today, the arrangement is very compact. But by stacking the transistors and adjusting the interconnects, the inverter’s area was cut in half.
Intel stacked nanosheet transistors

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Thomas De Maesschalck

Thomas has been messing with computer since early childhood and firmly believes the Internet is the best thing since sliced bread. Enjoys playing with new tech, is fascinated by science, and passionate about financial markets. When not behind a computer, he can be found with running shoes on or lifting heavy weights in the weight room.

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