SK Hynix sees 600-layer NAND, EUV-based DRAM and CPUs with embedded NAND and RAM

Posted on Tuesday, Mar 23 2021 @ 14:33 CET by Thomas De Maesschalck
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SK hynix CEO Seok-Hee Lee talked about future memory developments at the Institute of Electrical and Electronics Engineers (IEEE) International Reliability Physics Symposium (IRPS). In a virtual keynote speech, details were provided about future NAND and DRAM products. Tom's Hardware has a nice summary over here.

The path to 600-layer NAND

First up, SK hynix expects it will be possible to significantly increase the number of layers used by 3D NAND flash memory. At the moment, the company is shipping NAND with 176-layers and SK hynix sees a path to devices that use 600 layers and beyond. A timeline was not provided and hitting 600-layers will require several technological advances.

Future DRAM will use EUV

Semiconductor chips are starting to adopt EUV lithography and this is a technology that will also find its way to the DRAM market. Just like its biggest rivals, SK hynix is certain that nodes that utilize EUV will help to increase performance, boost capacity, and lower energy consumption of future DRAM chips.

SK hynix predicts convergence of CPU, RAM and NAND

Last but not least, SK hynix expects future processors will have onboard DRAM and NAND flash memory. SK hynix CEO Seok-Hee Lee expects we'll first see a convergence to PIM (Processing In Memory), which means the memory is located on the same package as the CPU. Looking further into the future, the expectation is that we'll move to CIM (Computing in Memory). This final step will result in CPUs with on-die memory. SK hynix is not alone here, Samsung is researching similar technology.
CEO Lee predicted that semiconductor memories will develop toward a convergence of memory and logic to overcome the performance limitations, in the era of New ICT where all devices are integrated based on AI technology. This means that some of the computing functions of the central processing unit (CPU) are given to the DRAM functions. As the speed was increased in HBM by increasing the number of channels between the CPU and the memory, the speed will increase further in PNM (Processing Near Memory), where both the CPU and the memory exist within a single module. The speed will further increase in PIM (Processing In Memory), where the CPU and the memory exists within a single package. Ultimately, speed will increase further in CIM (Computing in Memory), where the CPU and the memory is integrated within in a single die, to deliver high performance computing system.




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Thomas De Maesschalck

Thomas has been messing with computer since early childhood and firmly believes the Internet is the best thing since sliced bread. Enjoys playing with new tech, is fascinated by science, and passionate about financial markets. When not behind a computer, he can be found with running shoes on or lifting heavy weights in the weight room.



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