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TSMC starts testing 65nm process

Posted on Thursday, October 06 2005 @ 15:02:07 CEST by

TSMC has successfully completed the first of three CyberShuttle prototype production runs for the company’s industry leading 65 nanometer Nexsys Technology for SoC. Five major customers’ designs and multiple 3rd party IP designs are on the first shuttle, which supports two different 65nm process options – the battery-saving Low Power process and the power-performance balanced General Purpose option.

The prototype launch opens the doors to 65nm prototyping work. Two more 65nm prototype shuttles will be launched by the end of 2005, and will include the Low Power, General Purpose and other enhancement process options. Bookings for all three shuttles are strong.

Beginning in 2006, TSMC will launch additional 65nm shuttles every other month, enabling customers and EDA, IP and library suppliers to prototype and qualify their leading-edge designs.

“The launch of the foundry industry’s first production prototype runs at the 65nm node realizes our commitment to make the Nexsys 65nm process available by the end of 2005,” said Jason Chen, vice president of corporate development at TSMC. “In addition, it allows our customers and third-party providers to get a jump on product development at this node. It’s also a clear indication that the industry is eager to utilize this technology.”

The 65nm CyberShuttles’ high utilization rates are indicative that several major companies are well into their 65nm development efforts and are ready to tape out. The tape-outs include a range of products, nearly all of which support wired and wireless consumer electronics applications.

Among the companies aboard this groundbreaking first run are Altera, Broadcom, and Freescale.

TSMC’s 65nm Nexsys technology is the company’s third-generation semiconductor process employing both copper interconnects and low-k dielectrics. The new process technology enables a standard cell gate density twice that of TSMC’s Nexsys 90nm process with a very competitive 6T SRAM and a 1T memory cell size. It also features an aggressive gate oxide thickness to further enhance transistor performance.

TSMC’s 65nm success builds on the company’s industry leading 0.13-micron and 90nm track records. TSMC estimates that the 65nm production will start to ramp up by the second quarter of 2006.



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