TSMC says 2nm progress is going nicely

Posted on Tuesday, April 27 2021 @ 11:44 CEST by Thomas De Maesschalck
AnandTech took an in-depth look at TSMC's roadmap, quite a lot of interesting tidbits in this article. TSMC recently provided an update about where it stands with upcoming nodes.

N5 yields better than expected

First up, N5 is gaining customers and is expected to account for about 20 percent of TSMC's wafer revenue of 2021. N5 is already in its second year of production, and according to TSMC, yields are better than originally expected. Production capacity will be expanded and soon the firm will roll out its N5P node, which promises 5 percent higher frequencies or 10 percent lower power consumption.

AnandTech cites a report from China Renaissance to draw some comparisons with nodes offered by competitors:
It is not particularly surprising that TSMC's N5 is gaining market share among adopters of leading-edge technologies. Analysts from China Renaissance estimate that TSMC's N5 features a transistor density of around 170 million transistors per square millimeter (MTr/mm2), which if accurate, makes it the densest technology available today. By contrast, Samsung's Foundry's 5LPE can boast with about 125 MTr/mm2 ~130 MTr/mm2, whereas Intel's 10 nm features an approximately 100 MTr/mm2 density.

N4 mass production next year

Next, we have N4. This is a further enhanced version of N5. The 4nm node is expected to enter risk production later this year, with mass production expected in 2022.

N3 also in 2022

Besides N4, TSMC will also roll out its new N3 process node in 2022. This new technology will stick with FinFET transistors and promises 10-15 percent higher performance, or 25-30 percent lower power consumption. Transistor density will increase by a factor of 1.1 to 1.7x 1.1X for analog, 1.2X for SRAM, 1.7X for logic). N3 will keep using DUV lithography but will adopt EUV for more layers. Mass production of 3nm chips is expected in the second half of 2022.

N2 and beyond

To maintain its leadership position, TSMC is investing a lot of money into R&D. Future nodes will use gate-all-around FETs (GAAFETs), this technique may be introduced with the N2 node. This is a bit further into the future, but TSMC says the 2nm process is already coming along nicely:
"For advanced CMOS logic, TSMC’s 3nm and 2nm CMOS nodes are progressing nicely through the pipeline," the company said in its annual report recently. "In addition, TSMC's reinforced exploratory R&D work is focused on beyond-2nm node and on areas such as 3D transistors, new memory and low-R interconnect, which are on track to establish a solid foundation to feed into many technology platforms.
Over the next three years, TSMC will invest $100 billion to expand production capacity and keep its edge over the rest of the industry.

About the Author

Thomas De Maesschalck

Thomas has been messing with computer since early childhood and firmly believes the Internet is the best thing since sliced bread. Enjoys playing with new tech, is fascinated by science, and passionate about financial markets. When not behind a computer, he can be found with running shoes on or lifting heavy weights in the weight room.

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