Interestingly, it seems AMD planned ahead for this for quite some time. TechInsights analyst Yuzo Fukuzaki discovered the existing Zen 3-based processors were designed with 3D V-Cache in mind. An examination of the Ryzen 9 5950X processor revealed this chip has unused connections that will be used for V-Cache:
There’s a row of dots in the image above. AMD uses TSVs — Through Silicon Vias — to connect the L3 cache directly to the CPU. That’s where the TSVs will run in future V-Cache CPUs. AMD didn’t respin Zen 3 to add V-Cache; it designed the chip to be augmented in this fashion before Zen 3 ever shipped. This kind of forward-looking design is what helps a semiconductor firm execute a regular cadence. Intel has historically dominated the chip industry partly because it mastered this concept and branded it as Tick-Tock. AMD isn’t copying Intel’s old strategy of node shrinks and new architectural improvements, but the company is clearly thinking multiple steps ahead.