AMD shows path to direct circuit slicing for 3D packaging

Posted on Monday, August 23 2021 @ 14:37 CEST by Thomas De Maesschalck
At the Hot Chips 33 conference, AMD revealed details about its future packaging technology. First up, we learn that the TSV connections used for AMD's upcoming CPUs with 3D Vertical Cache are a lot denser than what's currently used.

AMD's 3D V-Cache uses a 9 micron pitch, which is slightly smaller than the 10 micron pitch used by Intel's Foveros Direct technology, which will debut in 2023.

At the moment, 3D chip stacking allows full die-to-die stacking, but in the future it will be possible to allow macroblocks to be stacked. AnandTech's Ian Cutress points out the future is direct circuit slicing, once the TSV pitch is dense enough to make this possible.
Eventually, the TSV pitch will be so dense that module splitting, folding or even circuit splitting will be possible, which will completely revamp the future of processors as we know them today. AMD listed all existing stacking technologies, including Intel’s Foveros/EMIB techniques, implying that AMD considered using this technology for their processors...

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Thomas De Maesschalck

Thomas has been messing with computer since early childhood and firmly believes the Internet is the best thing since sliced bread. Enjoys playing with new tech, is fascinated by science, and passionate about financial markets. When not behind a computer, he can be found with running shoes on or lifting heavy weights in the weight room.

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