TSMC 3nm... when the SRAM scaling stops

XDA Developers offers a hot take on the recent news about TSMC's 3nm process technology. One of the profound implications of TSMC's latest process technology seems to be that historical scaling is officially dead. According to TSMC's own figures, the 3NE node will have exactly the same SRAM cache density as its 5nm predecessor.

The 3NB node, which is more of a niche product, will have some SRAM scaling. But even that node's SRAM scaling will be a mere 5 percent better than 5nm. Chip-level transistor scaling is still 1.6x and 1.7x for N3B and N3E, but overall it's bad news for Moore's Law as shrinking chips is becoming increasingly more complex.

But the problem isn't just about not being able to increase the amount of cache without using up more area. Processors can only be so large, and any space taken up by cache is space that can't be used for logic, or the transistors that lead to direct performance gains. At the same time, processors with more cores and other features need more cache to avoid memory-related bottlenecks. Even though the density of logic continues to increase with every new node, it might not be enough to compensate for the lack of SRAM scaling. This might be the killing blow for Moore's Law.